intel 8085 microprocessor

Intel 8085 microprocessor architecture
Memory
Program, data and stack memories occupy the same memory space. The total addressable memory
size is 64 KB.
Program memory - program can be located anywhere in memory. Jump, branch and call instructions
use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch
instructions use absolute addressing.
Data memory - the data can be placed anywhere as the 8085 processor always uses 16-bit
addresses.
Stack memory is limited only by the size of memory. Stack grows downward.
First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.
Interrupts
The 8085 microprocessor has 5 interrupts. They are presented below in the order of their priority
(from lowest to highest):
INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from
the bus one instruction, usually one of these instructions:
* One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into
stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with
the RST instruction).
* CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is
specified in the second and third bytes of the instruction.
RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of
the PC register into stack and branches to 2Ch (hexadecimal) address.
RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of
the PC register into stack and branches to 34h (hexadecimal) address.
RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of
the PC register into stack and branches to 3Ch (hexadecimal) address.
Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of
the PC register into stack and branches to 24h (hexadecimal) address.
All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and
RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
I/O ports
256 Input ports
256 Output ports
Registers
Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store
operations.
Flag is an 8-bit register containing 5 1-bit flags:
* Sign - set if the most significant bit of the result is set.
* Zero - set if the result is zero.
* Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
* Parity - set if the parity (the number of set bits in the result) is even.
* Carry - set if there was a carry during addition, or borrow during subtraction/comparison.
General registers:
* 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C
register contains low-order byte. Some instructions may use BC register as a data pointer.
* 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E
register contains low-order byte. Some instructions may use DE register as a data pointer.
* 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L
register contains low-order byte. HL register usually contains a data pointer used to reference
memory addresses.
Stack pointer is a 16 bit register. This register is always incremented/decremented by 2.
Program counter is a 16-bit register.
Instruction Set
Instruction set of Intel 8085 microprocessor consists of the following instructions:
* Data moving instructions.
* Arithmetic - add, subtract, increment and decrement.
* Logic - AND, OR, XOR and rotate.
* Control transfer - conditional, unconditional, call subroutine, return from subroutine and
restarts.
* Input/Output instructions.
* Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.
Addressing modes
Register - references the data in a register or in a register pair.
Register indirect - instruction specifies register pair containing address, where the data is located.
Direct.
Immediate - 8 or 16-bit data.

about static RAM

L2 Cache RAM Technology

As Intel continued to push the evolution of x86 PC's, it was growing evident that conventional memory technology was not enough. There wasn't enough RAM to cache large amounts of data, and the microprocessor was losing a lot of time to retrieving from the hard disk.

The answer was a Level 2 cache - something that could hold data close to the microprocessor for extremely high speed access without bothering the system RAM or hard disk. Typical RAM could not be used, however, as it required constant refreshing which was reducing performance. The answer was to create small amounts of heavily reinforced memory known as Static Ram. By keeping the electrons from dispersing, refresh cycles would are not needed.

Why "Level 2" Cache?

The level number is merely an indicator to how many caches are in a PC. The L1 cache is a small (64 kilobytes now) level of cache held on the microprocessor. The L2 cache is typically an external memory cache closely coupled to the microprocessor or system bus. In cases where an L2 cache exists on the CPU/Cartridge, as well as on the motherboard, the motherboard cache is called the L3 cache. This process continues on, although 3 levels of cache is usually the maximum.

Asynchronous Static RAM - Async SRAM

The cheapest and first type of SRAM. It operates asynchronously to the CPU, which causes it to be about 1/3rd as effective. However, for older machines it is great for a cheap speed boost.

Synchronous Burst Static RAM - Syncburst SRAM

The most expensive form of SRAM - with substantially lower latencies and a burst mode. As Tom's Hardware Guide explains, at a 66 MHz System Bus speed it is indeed the fastest form of SRAM, but as bus speeds move up, it essentially can't keep up. Intel uses a form of this type of RAM operating at 1/2 the CPU clock speed in their current Pentium II packages.

Pipeline Burst Static RAM

The most commonly used SRAM today. By employing I/O registers, it loses a cycle, but gains more speed for the next access. It is also generally twice again as fast as Syncburst SRAM. You will usually find this RAM on Socket 7 motherboards with sizes from 256k to 2 megabytes.

L2 Cache Size Issues

For most computers today, the L2 cache does not improve performance dramatically past 512 kilobytes. However, the L2 cache also helps in another key area - the cacheable RAM area. Doubling your L2 cache to 1 megabyte essentially doubles the amount of cacheable RAM your system can hold. L2 cache size is also relevant for server machines, as higher levels help maintain performance under high levels of processing demand while allowing the high amounts of system RAM servers usually need.

For the home user, the situation is a bit more complicated. L2 Cache does not make or break a microprocessor - so don't buy one by only looking at its cache. Intel currently has 3 types of Pentium IIs for the home market - Celeron CPUs with no L2, Celeron Pro CPUs with 128kb of full speed L2, and Pentium II's with 512kb of half speed L2. In actual benchmarks, however, the speed difference shows that the Celeron Pro matches closely to a P2. The Celeron falls behind in business related programs, but is relatively unaffected in games.

Differences between Slot One and Socket 7 Cache

After Intel abandoned the Socket 7 arena, the L2 cache question began to change. Previously, L2 cache was relegated to the motherboard in the form of modules which operated at the front side bus clock speed of the motherboard. Intel tried moving the L2 cache to the CPU die with the Pentium Pro (so it would operate at the CPU clock speed), as well as on a card adjacent to the microprocessor (for half CPU speed with the Pentium 2).

Processor	L2 Cache Max	Speed	Location
Intel 486	512 KB	FSB	Motherboard
Intel Pentium	512 KB	FSB	Motherboard
Intel Pentium Pro	1024 KB	CPU	Processor die
Intel Pentium 2	512 KB	1/2 CPU	Card PCB
Intel Celeron	0 KB	NA	NA
Intel Celeron Pro	128 KB	CPU	Processor die
Intel Xeon	2048 KB	CPU	Card PCB
AMD K6-2	2048 KB	FSB	Motherboard
AMD K6-3	256 KB	CPU	Processor die

In a strange about-face, Intel plans to move cache back onto the microprocessor die, in order to combat cache costs as well as fight against AMD's K6-3.

Upgrading L2 Cache - A rare occurrence

In the days of the Pentium, the L2 cache came in two sizes - 256 KB or 512 KB. Many motherboards opted for the former, while leaving expansion for the latter. COAST (Cache On A Stick) modules could be inserted like a CPU. The growing trend today, however, is to move the cache onto the processor die (K6-2, Pentium Pro, Celeron Pro), or onto the cartridge PCB (Pentium 2, Xeon). This gives the chip makers control over L2 cache speed and size

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